CMLDM7003 CMLDM7003g* CMLDM7003j surface mount dual n-channel enhancement-mode silicon mosfet description: these central semiconductor devices are dual enhancement-mode n-channel field effect transistors, manufactured by the n-channel dmos process, designed for high speed pulsed amplifier and driver applications. the CMLDM7003 utilizes the usa pinout configuration, while the CMLDM7003j utilizes the japanese pinout configuration. these devices offer low r ds(on) and esd protection up to 2kv. marking codes: CMLDM7003: c30 CMLDM7003g*: c3g CMLDM7003j: c3j maximum ratings: (t a =25c) symbol units drain-source voltage v ds 50 v drain-gate voltage v dg 50 v gate-source voltage v gs 12 v continuous drain current i d 280 ma maximum pulsed drain current i dm 1.5 a power dissipation (note 1) p d 350 mw power dissipation (note 2) p d 300 mw power dissipation (note 3) p d 150 mw operating and storage junction temperature t j , t stg -65 to +150 c thermal resistance ja 357 c/w electrical characteristics per transistor: (t a =25c unless otherwise noted) symbol test conditions min typ max units i gssf, i gssr v gs =5.0v 100 na i gssf, i gssr v gs =10v 2.0 a i gssf, i gssr v gs =12v 2.0 a i dss v ds =50v, v gs =0 50 na bv dss v gs =0, i d =10a 50 v v gs(th) v ds =v gs , i d =250a 0.49 1.0 v v sd v gs =0, i s =115ma 1.4 v r ds(on) v gs =1.8v, i d =50ma 1.6 3.0 r ds(on) v gs =2.5v, i d =50ma 1.3 2.5 r ds(on) v gs =5.0v, i d =50ma 1.1 2.0 g fs v ds =10v, i d =200ma 200 ms c rss v ds =25v, v gs =0, f=1.0mhz 5.0 pf c iss v ds =25v, v gs =0, f=1.0mhz 50 pf c oss v ds =25v, v gs =0, f=1.0mhz 25 pf notes: (1) ceramic or aluminum core pc board with copper mounting pad area of 4.0mm 2 (2) fr-4 epoxy pc board with copper mounting pad area of 4.0mm 2 (3) fr-4 epoxy pc board with copper mounting pad area of 1.4mm 2 * device is halogen free by design sot-563 case r6 (18-january 2010) www.centralsemi.com
CMLDM7003 CMLDM7003g* CMLDM7003j surface mount dual n-channel enhancement-mode silicon mosfet sot-563 case - mechanical outline lead code: 1) gate q1 2) source q1 3) drain q2 4) gate q2 5) source q2 6) drain q1 marking codes: CMLDM7003: c30 CMLDM7003g*: c3g lead code: 1) source q1 2) gate q1 3) drain q2 4) source q2 5) gate q2 6) drain q1 marking code: c3j pin configurations CMLDM7003 (usa pinout) CMLDM7003g* CMLDM7003j (japanese pinout) * device is halogen free by design www.centralsemi.com r6 (18-january 2010)
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